As the performance of information processing apparatuses, such as apparatuses and servers for the communication infrastructure, improves, the data rate of signal transmission/reception inside and outside the apparatuses increases.
As a reception circuit, there is known a reception circuit having a function (CDR: Clock and Data Recovery) to receive a data signal superimposed with a clock, determine the data signal at an appropriate timing, and recover data and the clock.
Because the clock is not yet recovered immediately at start data signal input, the reception circuit may not determine the data at an appropriate timing and thus will generate an error in output data. A time period from the start of data signal input until the output data has no error is called a look time of the CDR. As the performance of the CDR, the shorter the lock time, the more preferable the lock time is. In applications that perform burst transmission, it is particularly important to shorten the lock time.
The examples of the CDR include a burst mode CDR and a PLL (Phase Locked Loop)-based CDR.
The burst mode CDR, upon detection of an edge from a data signal, resets an oscillation of a VCO (Voltage Controller Oscillator) so as to cause the phase of a clock (recovered clock) output from the VCO to coincide with the phase of the data signal (for example, see Japanese Laid-open Patent Publication No. 2012-85142). In the burst mode CDR, because the recovered clock will synchronize with the data signal immediately after an edge of the data signal is detected, the lock time is short. However, in the burst mode CDR, the jitter of the data signal is applied to the recovered clock. In the burst mode CDR, because there is no correlation between the jitter of the data signal and the jitter of the recovered clock (asynchronous jitter), the effect of the jitter is large and the characteristics of the burst mode CDR will degrade.
On the other hand, the PLL-based CDR detects a phase difference between a data signal and a recovered clock and varies the oscillation frequency of a VCO in response to the phase difference, thereby causing the phase of the recovered clock to coincide with the phase of the data signal (for example, see Japanese Laid-open Patent Publication No. 03-62730). The PLL-based CDR includes a loop filter for suppressing high frequency noise, and thus has few problems of jitter unlike the burst mode CDR. However, in the PLL-based CDR, frequency synchronization between a data signal that is input during an initial operation and a recovered clock takes a relatively long time, a tracking error is generated, and the lock time is increased.
If the CDR is simply switched to the PLL-based CDR after an initial operation in the burst mode CDR, in order to shorten the lock time while suppressing the effect of the jitter, then the phase of a clock shifts during the transition, a tracking error is generated, and frequency synchronization may not be established.